1. Field of the Invention
This disclosure relates to nonvolatile storage devices, and, in particular, to flash memory devices with an improved program algorithm, which is able to reduce program time.
2. Description of the Related Art
Semiconductor memories are usually considered to be the most vital microelectronic component of digital logic system design, such as computers and microprocessor-based applications ranging from satellites to consumer electronics. Therefore, advances in the fabrication of semiconductor memories including process enhancements and technology developments through the scaling for higher densities and faster speeds help establish performance standards for other digital logic families. Semiconductor memory devices may be characterized as either volatile random access memories (RAMs), or non-volatile memory devices. In RAMs, the logic information is stored either by setting up the logic state of a bistable flip-flop such as in a static random access memory (SRAM), or through the charging of a capacitor as in a dynamic random access memory (DRAM). In either case, the data is stored and can be read out as long as the power is applied, and the data is lost when the power is turned off; hence, they are called volatile memories.
Non-volatile memories, such as Mask Read-Only Memory (MROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM), are capable of storing the data, even with the power turned off. The non-volatile memory data storage mode may be permanent or reprogrammable, depending upon the fabrication technology used. Non-volatile memories are used for program and microcode storage in a wide variety of applications in the computer, avionics, telecommunications, and consumer electronics industries. A combination of single-chip volatile as well as non-volatile memory storage modes is also available in devices such as non-volatile SRAM (nvSRAM) for use in systems that require fast, programmable non-volatile memory. In addition, dozens of special memory architectures have evolved which contain some additional logic circuitry to optimize their performance for application-specific tasks.
In non-volatile memories, however, MROM, PROM, and EPROM are not free to be erased and written to by a system itself, so that it is not easy for general users to update stored contents. On the other hand, EEPROM is capable of electrically being erased or written. Application of the EEPROM is widened to an auxiliary memory or to system programming where continuous update is needed. In particular, a flash EEPROM (hereinafter, referred to as a flash memory) has a higher integration of degree than a conventional EEPROM and thus is advantageous to application to a large auxiliary memory.
A flash memory device includes a memory cell array that includes a number of memory blocks. A read/erase/program operation of respective memory blocks is made individually. The time required to erase memory blocks is a factor that limits the performance of a system that includes flash memory devices as well as a factor that limits the performance of the flash memory device itself.
To solve this drawback, a technique for simultaneously erasing a plurality of memory blocks is disclosed in U.S. Pat. No. 5,841,721 entitled “MULTI-BLOCK ERASE AND VERIFICATION CIRCUIT IN A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND A METHOD THEREOF” and U.S. Pat. No. 5,999,446 entitled “MULTI-STATE FLASH EEPROM SYSTEM WITH SELECTIVE MULTI-SECTOR ERASE”, which are herein incorporated by reference.
After simultaneously erasing a number of memory blocks, an erase verify operation is performed to judge whether the memory blocks have been normally erased. Such an erase verify operation is made with respect to each of simultaneously erased memory blocks. With the above references, the erase verify operation is carried out by storing address information of erased memory blocks in a memory device and referring to the stored address information. This means that a flash memory device requires separate control logic for controlling a multi-block erase verify operation and control signal lines related thereto. Accordingly, the erase verify operation of respective erased memory blocks is a factor that limits the performance and area of a flash memory device.
Embodiments of the invention address these and other disadvantages of the conventional art.